83 search results - page 7 / 17 » Technology Mapping for Reliability Enhancement in Logic Synt... |
80
Voted
ICCAD
2009
IEEE
14 years 7 months ago
2009
IEEE
As CMOS devices are scaled down into the nanometer regime, concerns about reliability are mounting. Instead of viewing nanoscale characteristics as an impediment, technologies suc...
71
Voted
TCAD
2008
14 years 9 months ago
2008
Boolean matching is one of the enabling techniques for technology mapping and logic resynthesis of Field Programmable Gate Array (FPGA). SAT-based Boolean matching (SAT-BM) has bee...
SAT
2007
Springer
15 years 3 months ago
2007
Springer
SAT solvers are often challenged with very hard problems that remain unsolved after hours of CPU time. The research community meets the challenge in two ways: (1) by improving the ...
91
Voted
ICCAD
1995
IEEE
15 years 1 months ago
1995
IEEE
ng certain electrical noise and power constraints.Abstract: We present a new delay model for use in logic synthesis. A traditional model treats the area of a library cell as consta...
FPGA
2006
ACM
15 years 1 months ago
2006
ACM
The high unit cost of FPGA devices often deters their use beyond the prototyping stage. Efforts have been made to reduce the part-cost of FPGA devices, resulting in the developmen...