62 search results - page 2 / 13 » Technology mapping for k m-macrocell based FPGAs |
ASPDAC
2004
ACM
13 years 11 months ago
2004
ACM
FPGA
2006
ACM
13 years 10 months ago
2006
ACM
The paper presents several improvements to state-of-theart in FPGA technology mapping exemplified by a recent advanced technology mapper DAOmap [Chen and Cong, ICCAD `04]. Improve...
GLVLSI
1998
IEEE
13 years 10 months ago
1998
IEEE
A new technology mapper SELF-Map for LookUp Table LUT based Field Programmable Gate Arrays FPGAs is described. SELF-Map is based on the Stochastic Evolution SE algorithm. The stat...
EH
2004
IEEE
13 years 10 months ago
2004
IEEE
Field programmable gate arrays (FPGAs) are becoming increasingly important implementation platforms for digital circuits. One of the necessary requirements to effectively utilize ...
ICCAD
1994
IEEE
13 years 10 months ago
1994
IEEE
We consider the problem of performance driven lookup-table (LUT) based technology mapping for FPGAs using a general delay model. In the general delay model, each interconnection e...