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» Temperature-aware routing in 3D ICs
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ISPD
2012
ACM
283views Hardware» more  ISPD 2012»
12 years 1 months ago
Low-power gated bus synthesis for 3d ic via rectilinear shortest-path steiner graph
In this paper, we propose a new approach for gated bus synthesis [16] with minimum wire capacitance per transaction in three-dimensional (3D) ICs. The 3D IC technology connects di...
Chung-Kuan Cheng, Peng Du, Andrew B. Kahng, Shih-H...
DAC
2011
ACM
12 years 6 months ago
Thermal-aware cell and through-silicon-via co-placement for 3D ICs
Existing thermal-aware 3D placement methods assume that the temperature of 3D ICs can be optimized by properly distributing the power dissipations, and ignoring the heat conductiv...
Jason Cong, Guojie Luo, Yiyu Shi
ASPDAC
2006
ACM
166views Hardware» more  ASPDAC 2006»
14 years 7 days ago
Temperature-aware routing in 3D ICs
Three-dimensional integrated circuits (3D ICs) provide an attractive solution for improving circuit performance. Such solutions must be embedded in an electrothermally-conscious d...
Tianpei Zhang, Yong Zhan, Sachin S. Sapatnekar
DATE
2009
IEEE
161views Hardware» more  DATE 2009»
14 years 1 months ago
Co-design of signal, power, and thermal distribution networks for 3D ICs
— Heat removal and power delivery are two major reliability concerns in the 3D stacked IC technology. Liquid cooling based on micro-fluidic channels is proposed as a viable solu...
Young-Joon Lee, Yoon Jo Kim, Gang Huang, Muhannad ...
ASPDAC
2005
ACM
86views Hardware» more  ASPDAC 2005»
13 years 12 months ago
Thermal-driven multilevel routing for 3-D ICs
3-D IC has a great potential for improving circuit performance and degree of integration. It is also an attractive platform for system-on-chip or system-in-package solutions. A cr...
Jason Cong, Yan Zhang