475 search results - page 47 / 95 » Temporal Logic Model Checking (Abstract) |
110
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CAV
2005
Springer
15 years 7 months ago
2005
Springer
Bounded model checking is an efficient method for finding bugs in system designs. The major drawback of the basic method is that it cannot prove properties, only disprove them. R...
183
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LICS
2003
IEEE
15 years 6 months ago
2003
IEEE
Probability features increasingly often in software and hardware systems: it is used in distributed co-ordination and routing problems, to model fault-tolerance and performance, a...
GLVLSI
2009
IEEE
15 years 8 months ago
2009
IEEE
In the context of formal verification Bounded Model Checking (BMC) has shown to be very powerful for large industrial designs. BMC is used to check whether a circuit satisfies a...
106
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CAV
2001
Springer
15 years 6 months ago
2001
Springer
In formal verification, we verify that a system is correct with respect to a specification. When verification succeeds and the system is proven to be correct, there is still a q...
114
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TACAS
2000
Springer
15 years 5 months ago
2000
Springer
This paper reports on experimental results with symbolic model checking of probabilistic processes based on Multi-Terminal Binary Decision Diagrams (MTBDDs). We consider concurrent...