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» Temporal Logic Model Checking (Abstract)
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IPPS
2006
IEEE
15 years 7 months ago
Formal modeling and analysis of wireless sensor network algorithms in Real-Time Maude
Advanced wireless sensor network algorithms pose challenges to their formal modeling and analysis, such as modeling probabilistic and real-time behaviors and novel forms of commun...
Peter Csaba Ölveczky, Stian Thorvaldsen
ASYNC
2005
IEEE
118views Hardware» more  ASYNC 2005»
15 years 7 months ago
Modeling and Verifying Circuits Using Generalized Relative Timing
We propose a novel technique for modeling and verifying timed circuits based on the notion of generalized relative timing. Generalized relative timing constraints can express not ...
Sanjit A. Seshia, Randal E. Bryant, Kenneth S. Ste...
ET
2010
98views more  ET 2010»
14 years 12 months ago
MONSOON: SAT-Based ATPG for Path Delay Faults Using Multiple-Valued Logics
Abstract As technology scales down into the nanometer era, delay testing of modern chips has become more and more important. Tests for the path delay fault model are widely used to...
Stephan Eggersglüß, Görschwin Fey,...
SACMAT
2009
ACM
15 years 7 months ago
Towards formal security analysis of GTRBAC using timed automata
An access control system is often viewed as a state transition system. Given a set of access control policies, a general safety requirement in such a system is to determine whethe...
Samrat Mondal, Shamik Sural, Vijayalakshmi Atluri
LICS
1998
IEEE
15 years 5 months ago
Existential Second-Order Logic over Strings
d abstract) T. Eiter G. Gottlob Y. Gurevich Institut fur Informatik Institut fur Informationssysteme EECS Department Universitat Gie en Technische Universitat Wien University of Mi...
Thomas Eiter, Georg Gottlob, Yuri Gurevich