203 search results - page 13 / 41 » Temporal Logic Verification Using Simulation |
KBSE
1999
IEEE
15 years 4 months ago
1999
IEEE
This paper describes the application of advanced formal modelling techniques and tools from the CADP toolset to the verification of CFS, a distributed file system kernel. After a ...
CORR
2010
Springer
14 years 11 months ago
2010
Springer
We introduce a generic extension of the popular branching-time logic CTL which refines the temporal until and release operators with formal languages. For instance, a language may ...
123
click to vote
DAC
2004
ACM
15 years 3 months ago
2004
ACM
This paper presents new technology that accelerates system verification. Traditional methods for verifying functional designs are based on logic simulation, which becomes more tim...
132
click to vote
RV
2010
Springer
14 years 9 months ago
2010
Springer
The RV system is the first system to merge the benefits of Runtime Monitoring with Predictive Analysis. The Runtime Monitoring portion of RV is based on the successful Monitoring O...
ICCAD
1999
IEEE
15 years 4 months ago
1999
IEEE
We introduce a new method of verifying the timing of custom CMOS circuits. Due to the exponential number of patterns required, traditional simulation methods are unable to exhaust...