203 search results - page 19 / 41 » Temporal Logic Verification Using Simulation |
102
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ICCD
2008
IEEE
15 years 8 months ago
2008
IEEE
—One of the major design verification challenges in the development of Anton, a massively parallel special-purpose machine for molecular dynamics, was to provide evidence that co...
101
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DAC
2008
ACM
16 years 23 days ago
2008
ACM
C++ based verification methodologies are now emerging as the preferred method for SOC design. However most of the verification involving the C++ models are simulation based. The c...
100
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WWW
2002
ACM
16 years 13 days ago
2002
ACM
HTML documents composed of frames can be difficult to write correctly. We demonstrate a technique that can be used by authors manually creating HTML documents (or by document edit...
106
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BPM
2009
Springer
15 years 27 days ago
2009
Springer
Abstract. Mainstream workflow management systems are using procedural languages ranging from BPMN and EPCs to BPEL and YAWL. By demonstrating DECLARE, we will show that it is also ...
DAC
2005
ACM
16 years 22 days ago
2005
ACM
We describe IODINE, a tool to automatically extract likely design properties using dynamic analysis. A practical bottleneck in the formal verification of hardware designs is the n...