203 search results - page 20 / 41 » Temporal Logic Verification Using Simulation |
114
click to vote
ATVA
2008
Springer
15 years 1 months ago
2008
Springer
Model checking has proven to be a useful analysis technique not only for concurrent systems, but also for the genetic regulatory networks (Grns) that govern the functioning of livi...
WSC
1994
15 years 1 months ago
1994
ABSTRACT This paper provides beginning and intermediate simulation practitioners and interested simulation consumers with a grounding in how discrete-event simulation software work...
LREC
2010
15 years 1 months ago
2010
We present CAVaT, a tool that performs Corpus Analysis and Validation for TimeML. CAVaT is an open source, modular checking utility for statistical analysis of features specific t...
115
click to vote
FMCAD
1998
Springer
15 years 4 months ago
1998
Springer
We present a new approach to the verification of hardware systems with data dependencies using temporal logic symbolic model checking. As a benchmark we take Tomasulo's algori...
FOAL
2009
ACM
15 years 3 months ago
2009
ACM
In this paper we specify an operational run-time semantics of Assignment Featherweight Java -- a minimal subset of Java with assignments -- with around advice, using graph transfo...