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» Temporal Logic Verification Using Simulation
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ISORC
2000
IEEE
15 years 3 months ago
Verification of UML-Based Real-Time System Designs by Means of cTLA
The Unified Modeling Language UML is well-suited for the design of real-time systems. In particular, the design of dynamic system behaviors is supported by interaction diagrams an...
Günter Graw, Peter Herrmann, Heiko Krumm
COORDINATION
2009
Springer
16 years 9 days ago
Assume-Guarantee Verification of Concurrent Systems
Process algebras are a set of mathematically rigourous languages with well defined semantics that permit modelling behaviour of concurrent and communicating systems. Verification o...
Liliana D'Errico, Michele Loreti
IJCAI
2003
15 years 1 months ago
Formal Verification of Diagnosability via Symbolic Model Checking
This paper addresses the formal verification of diagnosis systems. We tackle the problem of diagnosability: given a partially observable dynamic system, and a diagnosis system obs...
Alessandro Cimatti, Charles Pecheur, Roberto Cavad...
PADS
2009
ACM
15 years 6 months ago
An Approach for Validation of Semantic Composability in Simulation Models
Semantic composability aims to ensure that the composition of simulation components is meaningful in terms of their expressed behavior, and achieves the desired objective of the n...
Claudia Szabo, Yong Meng Teo
ASWEC
2006
IEEE
15 years 5 months ago
Formal Verification of the IEEE 802.11i WLAN Security Protocol
With the increased usage of wireless LANs (WLANs), businesses and educational institutions are becoming more concerned about wireless network security. The latest WLAN security pr...
Elankayer Sithirasenan, Saad Zafar, Vallipuram Mut...