203 search results - page 24 / 41 » Temporal Logic Verification Using Simulation |
111
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CODES
2008
IEEE
15 years 1 months ago
2008
IEEE
SystemC is widely used for modeling and simulation in hardware/software co-design. Due to the lack of a complete formal semantics, it is not possible to verify SystemC designs. In...
RE
2001
Springer
15 years 4 months ago
2001
Springer
A logic model checker can be an effective tool for debugging software applications. A stumbling block can be that model checking tools expect the user to supply a formal statement...
134
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CADE
2008
Springer
16 years 2 days ago
2008
Springer
Many safety- and security-critical systems are real-time systems and, as a result, tools and techniques for verifying real-time systems are extremely important. Simulation and test...
ENTCS
2006
14 years 11 months ago
2006
Klaim is an experimental language designed for modeling and programming distributed systems composed of mobile components where distribution awareness and dynamic system architect...
108
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ASE
2005
14 years 11 months ago
2005
Techniques for efficiently evaluating future time Linear Temporal Logic (abbreviated LTL) formulae on finite execution traces are presented. While the standard models of LTL are i...