203 search results - page 26 / 41 » Temporal Logic Verification Using Simulation |
195
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ICDT
2009
ACM
16 years 13 days ago
2009
ACM
We formalize and study business process systems that are centered around "business artifacts", or simply "artifacts". This approach focuses on data records, kn...
ECAI
2004
Springer
15 years 5 months ago
2004
Springer
To enable the development of automated support for the dynamics of design processes, a challenge is to model and analyse such dynamics in a formal manner. This paper contributes a ...
100
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TCAD
2002
14 years 11 months ago
2002
Many tasks in CAD, such as equivalence checking, property checking, logic synthesis, and false paths analysis require efficient Boolean reasoning for problems derived from circuits...
102
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AOSE
2005
Springer
15 years 5 months ago
2005
Springer
In order to create adaptive Agent Systems with abilities matching those of their biological counterparts, a natural approach is to incorporate classical conditioning mechanisms int...
199
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POPL
2005
ACM
16 years 1 days ago
2005
ACM
on Predicate Abstraction and Fair Termination Andreas Podelski Andrey Rybalchenko Max-Planck-Institut f?ur Informatik Saarbr?ucken, Germany Predicate abstraction is the basis of m...