203 search results - page 31 / 41 » Temporal Logic Verification Using Simulation |
FMCAD
2000
Springer
15 years 3 months ago
2000
Springer
BLIF is a hardware description language designed for the hierarchical description of sequential circuits. We give a denotational semantics for BLIF-MV, a popular dialect of BLIF, t...
DAC
2006
ACM
16 years 21 days ago
2006
ACM
SAT sweeping is a method for simplifying an AND/INVERTER graph (AIG) by systematically merging graph vertices from the inputs towards the outputs using a combination of structural...
JSAI
2005
Springer
15 years 5 months ago
2005
Springer
Abstract. This paper is concerned with algorithms for the logical generalisation of probabilistic temporal models from examples. The algorithms combine logic and probabilistic mode...
TODAES
2008
14 years 11 months ago
2008
Abstract-- Automata-based methods for generating PSL hardware assertion checkers were primarily considered for use with temporal sequences, as opposed to full-scale properties. We ...
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FAABS
2004
Springer
15 years 5 months ago
2004
Springer
Abstract. The design of reactive systems must comply with logical correctness (the system does what it is supposed to do) and timeliness (the system has to satisfy a set of tempora...