203 search results - page 32 / 41 » Temporal Logic Verification Using Simulation |
JUCS
2008
14 years 11 months ago
2008
: This paper gives a definition of ASM refinement suitable for the verification that a protocol implements atomic transactions. We used this definition as the basis of the formal v...
115
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UML
2004
Springer
15 years 5 months ago
2004
Springer
This paper discusses a model-based design flow for requirements in distributed embedded software development. Such requirements are specified using a language similar to Linear T...
SEFM
2005
IEEE
15 years 5 months ago
2005
IEEE
Experiments with simulators allow psychologists to better understand the causes of human errors and build models of cognitive processes to be used in Human Reliability Assessment ...
CODES
2008
IEEE
15 years 1 months ago
2008
IEEE
Functional validation is a major bottleneck in microprocessor design methodology. Simulation is the widely used method for functional validation using billions of random and biase...
115
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ICFEM
2010
Springer
14 years 10 months ago
2010
Springer
Abstract. Due to new emerging areas in the communication field there is a constant need for the design of novel communication protocols. This demands techniques for a rapid and eff...