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» Temporal Logic Verification Using Simulation
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AMOST
2007
ACM
15 years 3 months ago
Using LTL rewriting to improve the performance of model-checker based test-case generation
Model-checkers have recently been suggested for automated software test-case generation. Several works have presented methods that create efficient test-suites using model-checker...
Gordon Fraser, Franz Wotawa
TABLEAUX
1998
Springer
15 years 3 months ago
Model Checking: Historical Perspective and Example (Extended Abstract)
ple (Extended Abstract) Edmund M. Clarke and Sergey Berezin Carnegie Mellon University -- USA Model checking is an automatic verification technique for finite state concurrent syst...
Edmund M. Clarke, Sergey Berezin
ISQED
2002
IEEE
106views Hardware» more  ISQED 2002»
15 years 4 months ago
Trading off Reliability and Power-Consumption in Ultra-low Power Systems
Critical systems like pace-makers, defibrillators, wearable computers and other electronic gadgets have to be designed not only for reliability but also for ultra-low power consu...
Atul Maheshwari, Wayne Burleson, Russell Tessier
SIGSOFT
2001
ACM
16 years 14 days ago
Combining UML and formal notations for modelling real-time systems
This article explores a dual approach to real-time software development. Models are written in UML, as this is expected to be relatively easy and economic. Then models are automat...
Luigi Lavazza, Gabriele Quaroni, Matteo Venturelli
TIME
2006
IEEE
15 years 5 months ago
In time alone: on the computational power of querying the history
Querying its own history is an important mechanism in the computations, especially those interacting with people or other computations such as transaction processing, electronic d...
Alexei Lisitsa, Igor Potapov