203 search results - page 34 / 41 » Temporal Logic Verification Using Simulation |
DAC
2009
ACM
16 years 21 days ago
2009
ACM
Don't-care conditions provide additional flexibility in logic synthesis and optimization. However, most work only focuses on the gate level because it is difficult to handle ...
105
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DAC
2001
ACM
16 years 20 days ago
2001
ACM
This paper presents the design and evaluation of an 8-bit adiabatic multiplier. Both the multiplier core and its built-in self-test logic have been designed using a true single-ph...
MICRO
1999
IEEE
15 years 4 months ago
1999
IEEE
Building a high-performance microprocessor presents many reliability challenges. Designers must verify the correctness of large complex systems and construct implementations that ...
157
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FASE
2004
Springer
15 years 3 months ago
2004
Springer
Real-Time Maude is a language and tool supporting the formal specification and analysis of real-time and hybrid systems. The specification formalism is based on rewriting logic, em...
ICSE
2005
IEEE-ACM
15 years 11 months ago
2005
IEEE-ACM
Embedded systems are pervasive and frequently used for critical systems with time-dependent functionality. Dwyer et al. have developed qualitative specification patterns to facili...