203 search results - page 4 / 41 » Temporal Logic Verification Using Simulation |
SEW
2003
IEEE
15 years 2 months ago
2003
IEEE
Run-time monitoring is a lightweight verification method whereby the correctness of a programs’ execution is verified at run-time using executable specifications. This paper des...
WWW
2006
ACM
15 years 10 months ago
2006
ACM
The need of formal verification is a problem that involves all the fields in which sensible data are managed. In this context the verification of data streams became a fundamental...
AAAI
2004
14 years 11 months ago
2004
Model checking is a promising approach to automatic verification, which has concentrated on specification expressed in temporal logic. Comparatively little attention has been give...
SPIN
2000
Springer
15 years 1 months ago
2000
Springer
The Temporal Rover is a specification based verification tool for applications written in C, C++, Java, Verilog and VHDL. The tool combines formal specification, using Linear-Time ...
DAC
2006
ACM
15 years 3 months ago
2006
ACM
Architectural decisions for DSP modules are often analyzed using high level C models. Such high-level explorations allow early examination of the algorithms and the architectural ...