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SBCCI
2004
ACM
117views VLSI» more  SBCCI 2004»
15 years 4 months ago
Reducing test time with processor reuse in network-on-chip based systems
This paper proposes a test planning method capable of reusing available processors as test sources and sinks, and the on-chip network as the access mechanism for the test of cores...
Alexandre M. Amory, Érika F. Cota, Marcelo ...
DAC
1999
ACM
15 years 3 months ago
Test Generation for Gigahertz Processors Using an Automatic Functional Constraint Extractor
As the sizes of general and special purpose processors increase rapidly, generating high quality manufacturing tests which can be run at native speeds is becoming a serious proble...
Raghuram S. Tupuri, Arun Krishnamachary, Jacob A. ...
RTCSA
1998
IEEE
15 years 3 months ago
Protocol Synthesis from Context-Free Processes Using Event Structures
In this paper, we propose a protocol synthesis method based on a partial order model (called event structures) for the class of context-free processes. First, we assign a unique n...
Akio Nakata, Teruo Higashino, Kenichi Taniguchi
ECRTS
2004
IEEE
15 years 2 months ago
Managing Quality-of-Control Performance Under Overload Conditions
A common method for dealing with overload conditions in periodic task systems is to reduce the load by enlarging activation periods. When a periodic task implements a digital cont...
Giorgio C. Buttazzo, Manel Velasco, Pau Mart&iacut...
CPAIOR
2010
Springer
15 years 2 months ago
An In-Out Approach to Disjunctive Optimization
Cutting plane methods are widely used for solving convex optimization problems and are of fundamental importance, e.g., to provide tight bounds for Mixed-Integer Programs (MIPs). T...
Matteo Fischetti, Domenico Salvagnin