3221 search results - page 606 / 645 » Termination of Linear Programs |
164
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ICCAD
2006
IEEE
16 years 2 months ago
2006
IEEE
Parametric yield loss due to variability can be effectively reduced by both design-time optimization strategies and by adjusting circuit parameters to the realizations of variable...
123
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ICCAD
2006
IEEE
16 years 2 months ago
2006
IEEE
- Redundant via insertion and line end extension employed in the post-routing stage are two well known and highly recommended techniques to reduce yield loss due to via failure. Ho...
112
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ICCAD
2006
IEEE
16 years 2 months ago
2006
IEEE
Shallow trench isolation (STI) is the mainstream CMOS isolation technology. It uses chemical mechanical planarization (CMP) to remove excess of deposited oxide and attain a planar...
199
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ICCAD
2002
IEEE
16 years 2 months ago
2002
IEEE
Optimized solvers for the Boolean Satisfiability (SAT) problem have many applications in areas such as hardware and software verification, FPGA routing, planning, etc. Further use...
178
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ICDE
2010
IEEE
16 years 25 days ago
2010
IEEE
— To cope with bursty arrivals of high-volume data, a DSMS has to shed load while minimizing the degradation of Quality of Service (QoS). In this paper, we show that this problem...