3527 search results - page 209 / 706 » Test Automation in Practice |
132
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DAC
2003
ACM
16 years 5 months ago
2003
ACM
Functional verification is widely acknowledged as the bottleneck in the hardware design cycle. This paper addresses one of the main challenges of simulation based verification (or...
282
Voted
ICLP
2009
Springer
16 years 5 months ago
2009
Springer
Abstract. We present a framework that unifies unit testing and runtime verification (as well as static verification and static debugging). A key contribution of our overall approac...
141
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DATE
2000
IEEE
15 years 9 months ago
2000
IEEE
The Boolean satisfiability problem (SAT) has various applications in electronic design automation (EDA) fields such as testing, timing analysis and logic verification. SAT has bee...
112
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INTERACT
2003
15 years 5 months ago
2003
: If multiple evaluators analyse the outcomes of a single user test, the agreement between their lists of identified usability problems tends to be limited. This is called the ‘e...
159
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DAC
2008
ACM
16 years 5 months ago
2008
ACM
A SystemC simulation kernel consists of a deterministic implementation of the scheduler, whose specification is nondeterministic. To leverage testing of a SystemC TLM design, we f...