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DAC
2000
ACM
16 years 5 months ago
Convex delay models for transistor sizing
This paper derives a methodology for developing accurate convex delay models to be used for transistor sizing. A new rich class of convex functions to model gate delay is presente...
Mahesh Ketkar, Kishore Kasamsetty, Sachin S. Sapat...
DAC
2000
ACM
16 years 5 months ago
Symbolic timing simulation using cluster scheduling
We recently introduced symbolic timing simulation (STS) using data-dependent delays as a tool for verifying the timing of fullcustom transistor-level circuit designs, and for the ...
Clayton B. McDonald, Randal E. Bryant
DAC
2002
ACM
16 years 5 months ago
Unlocking the design secrets of a 2.29 Gb/s Rijndael processor
This contribution describes the design and performance testing of an Advanced Encryption Standard (AES) compliant encryption chip that delivers 2.29 GB/s of encryption throughput ...
Patrick Schaumont, Henry Kuo, Ingrid Verbauwhede
DAC
2002
ACM
16 years 5 months ago
IP delivery for FPGAs using Applets and JHDL
This paper introduces an FPGA IP evaluation and delivery system that operates within Java applets. The use of such applets allows designers to create, evaluate, test, and obtain F...
Michael J. Wirthlin, Brian McMurtrey
ISBI
2004
IEEE
16 years 5 months ago
A Closed-Form Method for Improving Inter-Subject Coherence in Diffusion Tensor Magnetic Resonance Imaging
A simple method is presented to reduce within-group inter-subject scatter in diffusion tensor magnetic resonance imaging (DT-MRI). By "borrowing strength" across co-regi...
Nicholas Lange, Derek Jones, Carlo Pierpaoli