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    DAC
    2008
    ACM
    130views Computer Architecture» more  DAC 2008»
    A framework for block-based timing sensitivity analysis
    16 years 3 days ago
    A framework for block-based timing sensitivity analysis
    Download  www.ece.umn.edu
    Since process and environmental variations can no longer be ignored in high-performance microprocessor designs, it is necessary to develop techniques for computing the sensitiviti...
    Sanjay V. Kumar, Chandramouli V. Kashyap, Sachin S...
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    DAC
    2007
    ACM
    115views Computer Architecture» more  DAC 2007»
    On-The-Fly Resolve Trace Minimization
    16 years 3 days ago
    On-The-Fly Resolve Trace Minimization
    Download  www.cs.tau.ac.il
    The ability of modern SAT solvers to produce proofs of unsatisfiability for Boolean formulas has become a powerful tool for EDA applications. Proofs are generated from a resolve t...
    Ohad Shacham, Karen Yorav
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    DAC
    1998
    ACM
    194views Computer Architecture» more  DAC 1998»
    A Case Study in Embedded System Design: An Engine Control Unit
    16 years 2 days ago
    A Case Study in Embedded System Design: An Engine Control Unit
    Download  embedded.eecs.berkeley.edu
    A number of techniques and software tools for embedded system design have been recently proposed. However, the current practice in the designer community is heavily based on manua...
    Alberto L. Sangiovanni-Vincentelli, Antonino Damia...
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    81
    Voted
    DAC
    1999
    ACM
    130views Computer Architecture» more  DAC 1999»
    Hypergraph Partitioning for VLSI CAD: Methodology for Heuristic Development, Experimentation and Reporting
    16 years 2 days ago
    Hypergraph Partitioning for VLSI CAD: Methodology for Heuristic Development, Experimentation and Reporting
    Download  vlsicad.ucsd.edu
    We illustrate how technical contributions in the VLSI CAD partitioning literature can fail to provide one or more of: (i) reproducible results and descriptions, (ii) an enabling a...
    Andrew E. Caldwell, Andrew B. Kahng, Andrew A. Ken...
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    82
    Voted
    DAC
    1999
    ACM
    147views Computer Architecture» more  DAC 1999»
    Noise-Aware Repeater Insertion and Wire-Sizing for On-Chip Interconnect Using Hierarchical Moment-Matching
    16 years 2 days ago
    Noise-Aware Repeater Insertion and Wire-Sizing for On-Chip Interconnect Using Hierarchical Moment-Matching
    Download  vlsi.ece.wisc.edu
    Recently, several algorithms for interconnect optimization via repeater insertion and wire sizing have appeared based on the Elmore delay model. Using the Devgan noise metric [6] ...
    Chung-Ping Chen, Noel Menezes
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