1016 search results - page 2 / 204 » Test Generation for Designs with On-Chip Clock Generators |
ICCD
2004
IEEE
14 years 3 months ago
2004
IEEE
In this paper, we present an infrastructure IP core to facilitate on-chip clock jitter measurement. In the proposed approach, the clock signal under test is delayed by two differe...
DATE
2000
IEEE
13 years 10 months ago
2000
IEEE
In this paper, we present a BIST scheme for testing onchip AD and DA converters. We discuss on-chip generation of linear ramps as test stimuli, and propose techniques for measurin...
ITC
1997
IEEE
13 years 10 months ago
1997
IEEE
- An all-digital technique for the measurement of the jitter transfer function of charge-pump phase-locked loops is introduced. Input jitter may be generated using one of two metho...
HPCA
2003
IEEE
14 years 6 months ago
2003
IEEE
As the level of chip integration continues to advance at a fast pace, the desire for efficient interconnects-whether on-chip or off-chip--is rapidly increasing. Traditional interc...
DATE
2005
IEEE
13 years 12 months ago
2005
IEEE
Multi-channel waveform monitoring technique enhances built-in test and diagnostic capability of mixed-signal VLSI circuits. An 8-channel prototype system incorporates adaptive sam...