77 search results - page 10 / 16 » Test Generation for Global Delay Faults |
ATS
2003
IEEE
15 years 2 months ago
2003
IEEE
A new technique for synthesizing totally symmetric Boolean functions is presented that achieves complete robust path delay fault testability. We apply BDDs for the synthesis of sy...
86
Voted
ASPDAC
2006
ACM
15 years 3 months ago
2006
ACM
– We propose an interconnect diagnosis scheme based on Oscillation Ring test methodology for SOC design with heterogeneous cores. The target fault models are delay faults and cro...
IFIP
2001
Springer
15 years 1 months ago
2001
Springer
: High defect coverage requires good coverage of different fault types. In this paper, we present a comprehensive test vector generation technique for BIST, called Random Single In...
VTS
2005
IEEE
15 years 3 months ago
2005
IEEE
This paper presents a pseudo-functional BIST scheme that attempts to minimize the over-testing problem of logic BIST for delay and crosstalk-induced failures. The over-testing pro...
ET
2006
14 years 9 months ago
2006
We present an efficient built-in self-test (BIST) architecture for testing and diagnosing stuck-at faults, delay faults, and bridging faults in FPGA interconnect resources. The BIS...