77 search results - page 12 / 16 » Test Generation for Global Delay Faults |
101
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ATS
2010
IEEE
14 years 7 months ago
2010
IEEE
Abstract--To achieve a high product quality for nano-scale systems both realistic defect mechanisms and process variations must be taken into account. While existing approaches for...
99
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VTS
2002
IEEE
15 years 2 months ago
2002
IEEE
We present a software-based weighted random pattern scheme for testing delay faults in IP cores of programmable SoCs. We describe a method for determining static and transition pr...
ICSM
2006
IEEE
15 years 3 months ago
2006
IEEE
The test case execution order affects the time at which the objectives of testing are met. If the objective is fault detection, an inappropriate execution order might reveal most ...
ITC
1997
IEEE
15 years 1 months ago
1997
IEEE
In a fundamental paradigm shift in system design, entire systems are being built on a single chip, using multiple embedded cores. Though the newest system design methodology has s...
DAC
1994
ACM
15 years 1 months ago
1994
ACM
A powerful combinational path sensitization engine is required for the efficient implementation of tools for test pattern generation, timing analysis, and delay fault testing. Path...