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EURODAC
1994
IEEE
148views VHDL» more  EURODAC 1994»
13 years 10 months ago
BiTeS: a BDD based test pattern generator for strong robust path delay faults
This paper presents an algorithm for generation of test patterns for strong robust path delay faults, i.e. tests that propagate the fault along a single path and additionally are ...
Rolf Drechsler
DDECS
2007
IEEE
90views Hardware» more  DDECS 2007»
13 years 10 months ago
Test Pattern Generator for Delay Faults
A method of generating test pairs for the delay faults is presented in this paper. The modification of the MISR register gives the source of test pairs. The modification of this r...
Tomasz Rudnicki, Andrzej Hlawiczka
DAC
2007
ACM
14 years 7 months ago
Transition Delay Fault Test Pattern Generation Considering Supply Voltage Noise in a SOC Design
Due to shrinking technology, increasing functional frequency and density, and reduced noise margins with supply voltage scaling, the sensitivity of designs to supply voltage noise...
Nisar Ahmed, Mohammad Tehranipoor, Vinay Jayaram
JISE
2000
68views more  JISE 2000»
13 years 6 months ago
Testable Path Delay Fault Cover for Sequential Circuits
We present an algorithm for identifyinga set of faults that do not have to be targeted by a sequential delay fault test generator. These faults either cannot independently aect th...
Angela Krstic, Srimat T. Chakradhar, Kwang-Ting Ch...
ATS
2003
IEEE
75views Hardware» more  ATS 2003»
13 years 11 months ago
An Enhanced Test Generator for Capacitance Induced Crosstalk Delay Faults
Capacitive crosstalk can give rise to slowdown of signals that can propagate to a circuit output and create a functional error. A test generation methodology, called XGEN, was dev...
Arani Sinha, Sandeep K. Gupta, Melvin A. Breuer