Sciweavers

77 search results - page 4 / 16
» Test Generation for Global Delay Faults
Sort
View
ETS
2006
IEEE
110views Hardware» more  ETS 2006»
15 years 3 months ago
Deterministic Logic BIST for Transition Fault Testing
BIST is an attractive approach to detect delay faults due to its inherent support for at-speed test. Deterministic logic BIST (DLBIST) is a technique which was successfully applie...
Valentin Gherman, Hans-Joachim Wunderlich, Jü...
VLSID
1995
IEEE
112views VLSI» more  VLSID 1995»
15 years 1 months ago
An efficient automatic test generation system for path delay faults in combinational circuits
Ananta K. Majhi, James Jacob, Lalit M. Patnaik, Vi...
ASPDAC
2008
ACM
78views Hardware» more  ASPDAC 2008»
14 years 11 months ago
Robust test generation for power supply noise induced path delay faults
Xiang Fu, Huawei Li, Yu Hu, Xiaowei Li
TODAES
1998
64views more  TODAES 1998»
14 years 9 months ago
Functional test generation for delay faults in combinational circuits
Irith Pomeranz, Sudhakar M. Reddy
DATE
2007
IEEE
83views Hardware» more  DATE 2007»
15 years 3 months ago
High-level test synthesis for delay fault testability
A high-level test synthesis (HLTS) method targeted for delay fault testability is presented. The proposed method, when combined with hierarchical test pattern generation for embed...
Sying-Jyan Wang, Tung-Hua Yeh