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» Test Pattern Generator for Delay Faults
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TODAES
1998
64views more  TODAES 1998»
14 years 9 months ago
Functional test generation for delay faults in combinational circuits
Irith Pomeranz, Sudhakar M. Reddy
VLSID
1995
IEEE
112views VLSI» more  VLSID 1995»
15 years 1 months ago
An efficient automatic test generation system for path delay faults in combinational circuits
Ananta K. Majhi, James Jacob, Lalit M. Patnaik, Vi...
ASPDAC
2008
ACM
78views Hardware» more  ASPDAC 2008»
14 years 11 months ago
Robust test generation for power supply noise induced path delay faults
Xiang Fu, Huawei Li, Yu Hu, Xiaowei Li
ICCAD
1998
IEEE
122views Hardware» more  ICCAD 1998»
15 years 1 months ago
Dynamic fault collapsing and diagnostic test pattern generation for sequential circuits
In this paper, we present results for significantly improving the performance of sequential circuit diagnostic test pattern generation (DATPG). Our improvements are achieved by de...
Vamsi Boppana, W. Kent Fuchs
TCAD
2002
106views more  TCAD 2002»
14 years 9 months ago
Design of hierarchical cellular automata for on-chip test pattern generator
This paper introduces the concept of hierarchical cellular automata (HCA). The theory of HCA is developed over the Galois extension field (2 ), where each cell of the CA can store ...
Biplab K. Sikdar, Niloy Ganguly, Parimal Pal Chaud...