203 search results - page 13 / 41 » Test Pattern Generator for Delay Faults |
138
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IOLTS
2005
IEEE
15 years 7 months ago
2005
IEEE
This paper proposes a new test pattern generator (TPG) which is an enhancement of GLFSR (Galois LFSR). This design is based on certain non–binary error detecting codes, formulat...
102
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ISCAS
1995
IEEE
15 years 5 months ago
1995
IEEE
: Configurations of adders and registers, which are available in tnany datapaths, can be utilized to generate pattems and to compact test responses. Thispaper unalyzes tlie patiern...
131
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VTS
2008
IEEE
15 years 8 months ago
2008
IEEE
Timing-related defects are becoming increasingly important in nanometer technology designs. Small delay variations induced by crosstalk, process variations, powersupply noise, as ...
114
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ICCAD
2002
IEEE
15 years 10 months ago
2002
IEEE
This work presents several new techniques for enhancing the performance of deterministic test pattern generation for VLSI circuits. The techniques introduced are called dynamic de...
117
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ASPDAC
2004
ACM
15 years 7 months ago
2004
ACM
- Under manufacturing process variation, a path through a fault site is called longest for delay test if there exists a process condition under which the path has the maximum delay...