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» Test Pattern Generator for Delay Faults
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ITC
2003
IEEE
120views Hardware» more  ITC 2003»
15 years 7 months ago
High Quality ATPG for Delay Defects
: The paper presents a novel technique for generating effective vectors for delay defects. The test set achieves high path delay fault coverage to capture smalldistributed delay de...
Puneet Gupta, Michael S. Hsiao
ATS
2003
IEEE
131views Hardware» more  ATS 2003»
15 years 7 months ago
Software-Based Delay Fault Testing of Processor Cores
Software-based self-testing is a promising approach for the testing of processor cores which are embedded inside a System-on-a-Chip (SoC), as it can apply test vectors in function...
Virendra Singh, Michiko Inoue, Kewal K. Saluja, Hi...
ETS
2009
IEEE
79views Hardware» more  ETS 2009»
14 years 11 months ago
Concurrent Self-Test with Partially Specified Patterns for Low Test Latency and Overhead
Structural on-line self-test may be performed to detect permanent faults and avoid their accumulation. This paper improves concurrent BIST techniques based on a deterministic test ...
Michael A. Kochte, Christian G. Zoellin, Hans-Joac...
DAC
1997
ACM
15 years 6 months ago
Automatic Generation of Synchronous Test Patterns for Asynchronous Circuits
This paper presents a novel approach for automatic test pattern generation of asynchronous circuits. The techniques used for this purpose assume that the circuit can only be exerc...
Oriol Roig, Jordi Cortadella, Marco A. Peña...
DATE
2009
IEEE
94views Hardware» more  DATE 2009»
15 years 8 months ago
Improving compressed test pattern generation for multiple scan chain failure diagnosis
To reduce test data volumes, encoded tests and compacted test responses are widely used in industry. Use of test response compaction negatively impacts fault diagnosis since the e...
Xun Tang, Ruifeng Guo, Wu-Tung Cheng, Sudhakar M. ...