203 search results - page 16 / 41 » Test Pattern Generator for Delay Faults |
165
click to vote
EVOW
1999
Springer
15 years 6 months ago
1999
Springer
A technique is proposed to reduce the peak power consumption of sequential circuits during test pattern application. High-speed computation intensive VLSI systems, as telecommunica...
116
click to vote
VTS
1995
IEEE
15 years 5 months ago
1995
IEEE
This paper presents a new approach for on-chip test pattern generation. The set of test patterns generated by a pseudo-random pattern generator (e.g., an LFSR) is transformed into...
111
click to vote
VTS
2000
IEEE
15 years 6 months ago
2000
IEEE
1 This paper addresses the problem of testing path delay faults in a microprocessor using instructions. It is observed that a structurally testable path (i.e., a path testable thro...
111
click to vote
ATS
2000
IEEE
15 years 6 months ago
2000
IEEE
At very high frequencies, the major potential of asynchronous circuits is absence of clock skew and, through that, better exploitation of relative timing relations. This paper pre...
145
click to vote
ATS
1998
IEEE
15 years 6 months ago
1998
IEEE
This paper presents a new effective Built-In Self Test (BIST) scheme that achieves 100% fault coverage with low area overhead, and without any modification of the circuit under tes...