203 search results - page 18 / 41 » Test Pattern Generator for Delay Faults |
ITC
1997
IEEE
15 years 5 months ago
1997
IEEE
This paper proposes an environment to address Testability Analysis and Test Pattern Generation on VHDL descriptions at the RT-level. The proposed approach, based on a suitable fau...
118
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DATE
2000
IEEE
15 years 6 months ago
2000
IEEE
This paper describes an efficient error simulator able to analyze functional VHDL descriptions. The proposed simulation environment can be based on commercial VHDL simulators. Al...
126
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ASPDAC
1998
ACM
15 years 6 months ago
1998
ACM
— Test Pattern Generation for combinational circuits entails the identification of primary input assignments for detecting each fault in a set of target faults. An extension to ...
100
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ASPDAC
1998
ACM
15 years 6 months ago
1998
ACM
−This paper describes a new redundant fault identification algorithm with Exclusive-OR circuit reduction. The experimental results using this algorithm with a FAN-based test patt...
116
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ISCAS
1999
IEEE
15 years 6 months ago
1999
IEEE
The main objectives of Built-In Self Test (BIST) are the design of test pattern generator circuits which achieve the highest fault coverage, require the shortest sequence of test ...