203 search results - page 25 / 41 » Test Pattern Generator for Delay Faults |
107
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ASPDAC
2004
ACM
15 years 7 months ago
2004
ACM
— This paper presents a SAT-based ATPG tool targeting on a path-oriented transition fault model. Under this fault model, a transition fault is detected through the longest sensit...
119
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ATS
2005
IEEE
15 years 7 months ago
2005
IEEE
The need for high-performance pipelined architectures has resulted in the adoption of latch based designs with multiple, interacting clocks. For such designs, time sharing across ...
DSD
2007
IEEE
15 years 8 months ago
2007
IEEE
Similar to sequential test pattern generation, the problem of identifying untestable faults in sequential circuits remains unsolved. Most of the previous works in untestability id...
122
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DSD
2005
IEEE
15 years 3 months ago
2005
IEEE
Several methods improving the fault coverage in mixed-mode BIST are presented in this paper. The test is divided into two phases: the pseudo-random and deterministic. Maximum of f...
106
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DAC
1997
ACM
15 years 6 months ago
1997
ACM
This paper presents a new scan-based BIST scheme which achieves very high fault coverage without the deficiencies of previously proposed schemes. This approach utilizes scan order...