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» Test Pattern Generator for Delay Faults
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DATE
2000
IEEE
130views Hardware» more  DATE 2000»
15 years 6 months ago
Optimal Hardware Pattern Generation for Functional BIST
∗∗ Functional BIST is a promising solution for self-testing complex digital systems at reduced costs in terms of area and performance degradation. The present paper addresses t...
Silvia Cataldo, Silvia Chiusano, Paolo Prinetto, H...
ICCD
2002
IEEE
108views Hardware» more  ICCD 2002»
15 years 10 months ago
Low Power Mixed-Mode BIST Based on Mask Pattern Generation Using Dual LFSR Re-Seeding
Low power design techniques have been employed for more than two decades, however an emerging problem is satisfying the test power constraints for avoiding destructive test and im...
Paul M. Rosinger, Bashir M. Al-Hashimi, Nicola Nic...
COMPSAC
1999
IEEE
15 years 6 months ago
Testing Extensible Design Patterns in Object-Oriented Frameworks through Scenario Templates
Design patterns have been used in object-oriented frameworks such as the IBM San Francisco framework, Apple's Rhaspody, OpenStep, and WebObjects, and DIWB. However, few guide...
Wei-Tek Tsai, Yongzhong Tu, Weiguang Shao, Ezra Eb...
VTS
1999
IEEE
106views Hardware» more  VTS 1999»
15 years 6 months ago
RT-level TPG Exploiting High-Level Synthesis Information
High-level test pattern generation is today a widely investigated research topic. The present paper proposes a fully automated, simulation-based ATPG system, to address test patte...
Silvia Chiusano, Fulvio Corno, Paolo Prinetto
ITC
1992
IEEE
76views Hardware» more  ITC 1992»
15 years 6 months ago
A Small Test Generator for Large Designs
In this paper we report an automatic test pattern generator that can handle designs with one million gates or more on medium size workstations. Run times and success rates, i.e. t...
Sandip Kundu, Leendert M. Huisman, Indira Nair, Vi...