203 search results - page 27 / 41 » Test Pattern Generator for Delay Faults |
113
Voted
ITC
1998
IEEE
15 years 6 months ago
1998
IEEE
This paper presents a logic synthesis tool called BETSY (BIST Environment Testable Synthesis) for synthesizing circuits that achieve complete (100%)fault coverage in a user specif...
103
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DELTA
2008
IEEE
15 years 8 months ago
2008
IEEE
Scan is a widely used design-for-testability technique to improve test and diagnosis quality, however, scan chain failures account for almost 50% of chip failures. In this paper, ...
132
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ATS
2000
IEEE
15 years 6 months ago
2000
IEEE
Because domino logic design offers smaller area and faster delay than conventional CMOS design, it is very popular in the high-performance processor design. However, domino logic ...
121
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ICES
2000
Springer
15 years 5 months ago
2000
Springer
Testing is a key issue in the design and production of digital circuits: the adoption of BIST (Built-In Self-Test) techniques is increasingly popular, but requires efficient algori...
136
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ITC
1994
IEEE
15 years 6 months ago
1994
IEEE
Previous approaches to designing random pattern testable circuits use post-synthesis test point insertion to eliminate random pattern resistant (r.p.r.) faults. The approach taken...