203 search results - page 30 / 41 » Test Pattern Generator for Delay Faults |
141
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INTEGRATION
2006
15 years 1 months ago
2006
Improving testability during the early stages of high-level synthesis has several benefits including reduced test hardware overheads, reduced test costs, reduced design iterations...
ITC
2003
IEEE
15 years 7 months ago
2003
IEEE
Energy Consumption Ratio (ECR) test, a current-based test, has shown its ability to reduce the impact of process variations and detect hard-to-detect faults. The effectiveness of ...
100
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DSD
2006
IEEE
15 years 8 months ago
2006
IEEE
Recently, a number of works have been published on implementing assignment decision diagram models combined with SAT methods to address register-transfer level test pattern genera...
121
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DAC
2000
ACM
16 years 2 months ago
2000
ACM
The effect of crosstalk errors is most significant in highperformance circuits, mandating at-speed testing for crosstalk defects. This paper describes a self-test methodology that...
DATE
2003
IEEE
15 years 7 months ago
2003
IEEE
Test pattern decompression techniques are bounded with the algorithm of test pattern ordering and test data flow controlling. Some of the methods could have more sophisticated sor...