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» Test Pattern Generator for Delay Faults
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CP
2009
Springer
16 years 11 days ago
Constraint-Based Optimal Testing Using DNNF Graphs
The goal of testing is to distinguish between a number of hypotheses about a systemfor example, dierent diagnoses of faults by applying input patterns and verifying or falsifying t...
Anika Schumann, Martin Sachenbacher, Jinbo Huang
SRDS
1993
IEEE
15 years 3 months ago
Bayesian Analysis for Fault Location in Homogeneous Distributed Systems
We propose a simple and practical probabilistic comparison-based model, employing multiple incomplete test concepts, for handling fault location in distributed systems using a Bay...
Yu Lo Cyrus Chang, Leslie C. Lander, Horng-Shing L...
ASPDAC
2005
ACM
142views Hardware» more  ASPDAC 2005»
15 years 1 months ago
Bridging fault testability of BDD circuits
Abstract— In this paper we study the testability of circuits derived from Binary Decision Diagrams (BDDs) under the bridging fault model. It is shown that testability can be form...
Junhao Shi, Görschwin Fey, Rolf Drechsler
ITC
2000
IEEE
84views Hardware» more  ITC 2000»
15 years 3 months ago
Non-intrusive BIST for systems-on-a-chip
1 The term "functional BIST" describes a test method to control functional modules so that they generate a deterministic test set, which targets structural faults within ...
Silvia Chiusano, Paolo Prinetto, Hans-Joachim Wund...
ICCAD
2002
IEEE
142views Hardware» more  ICCAD 2002»
15 years 8 months ago
SAT and ATPG: Boolean engines for formal hardware verification
In this survey, we outline basic SAT- and ATPGprocedures as well as their applications in formal hardware verification. We attempt to give the reader a trace trough literature and...
Armin Biere, Wolfgang Kunz