203 search results - page 38 / 41 » Test Pattern Generator for Delay Faults |
AAAI
2010
14 years 9 months ago
2010
The goal of testing is to discriminate between multiple hypotheses about a system--for example, different fault diagnoses--by applying input patterns and verifying or falsifying t...
DAC
2001
ACM
15 years 10 months ago
2001
ACM
We propose a new BDD-based method for decomposition of multi-output incompletely specified logic functions into netlists of two-input logic gates. The algorithm uses the internal ...
68
Voted
IJOE
2007
14 years 9 months ago
2007
: An environment targeted to e-learning is presented for teaching design and test of electronic systems. The environment consists of a set of Java applets, and of web based access ...
72
Voted
ITC
1999
IEEE
15 years 1 months ago
1999
IEEE
This paper discusses practical issues involved in applying logic built-in self-test (BIST) to four large industrial designs. These multi-clock designs, ranging in size from 200K t...
JSS
2008
14 years 8 months ago
2008
This report presents a model-driven, stress test methodology aimed at increasing chances of discovering faults related to network traffic in Distributed Real-Time Systems (DRTS). T...