203 search results - page 3 / 41 » Test Pattern Generator for Delay Faults |
ETS
2006
IEEE
15 years 3 months ago
2006
IEEE
BIST is an attractive approach to detect delay faults due to its inherent support for at-speed test. Deterministic logic BIST (DLBIST) is a technique which was successfully applie...
DATE
1997
IEEE
15 years 1 months ago
1997
IEEE
Many Built-In Self Test pattern generators use Linear Feedback Shift Registers (LFSR) to generate test sequences. In this paper, we address the generation of deterministic pairs o...
DATE
2007
IEEE
15 years 3 months ago
2007
IEEE
A high-level test synthesis (HLTS) method targeted for delay fault testability is presented. The proposed method, when combined with hierarchical test pattern generation for embed...
DAC
2006
ACM
15 years 10 months ago
2006
ACM
The delay fault test pattern set generated by timing unaware commercial ATPG tools mostly affects very short paths, thereby increasing the escape chance of smaller delay defects. ...
IOLTS
2000
IEEE
15 years 1 months ago
2000
IEEE
The combination of higher quality requirements and sensitivity of high performance circuits to delay defects has led to an increasing emphasis on delay testing of VLSI circuits. A...