203 search results - page 4 / 41 » Test Pattern Generator for Delay Faults |
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ISCAS
2007
IEEE
15 years 3 months ago
2007
IEEE
Due to the development of high speed circuits beyond the 2-GHz mark, the significance of automatic test pattern generation for Path Delay Faults (PDFs) drastically increased in t...
ASYNC
2006
IEEE
15 years 3 months ago
2006
IEEE
We propose a low-overhead method for delay fault testing in high-speed asynchronous pipelines. The key features of our work are: (i) testing strategies can be administered using l...
DATE
2008
IEEE
15 years 4 months ago
2008
IEEE
— Market and customer demands have continued to push the limits of CMOS performance. At-speed test has become a common method to ensure these high performance chips are being shi...
ASPDAC
2007
ACM
15 years 1 months ago
2007
ACM
- Two methods to apply tests to detect delay faults in standard scan designs are used. One is called launch off capture and the other is called launch off shift. Launch off shift t...
ASPDAC
2005
ACM
14 years 11 months ago
2005
ACM
Recent research results have shown that the traditional structural testing for delay and crosstalk faults may result in over-testing due to the non-trivial number of such faults t...