203 search results - page 7 / 41 » Test Pattern Generator for Delay Faults |
VTS
2002
IEEE
15 years 2 months ago
2002
IEEE
We present a software-based weighted random pattern scheme for testing delay faults in IP cores of programmable SoCs. We describe a method for determining static and transition pr...
68
Voted
VTS
2005
IEEE
15 years 3 months ago
2005
IEEE
TARO test patterns are transition fault test patterns that sensitize each transition fault to all of the outputs that can be reached from the fault location. We were not able to i...
103
Voted
ITC
1993
IEEE
15 years 1 months ago
1993
IEEE
This paper presents an efficient approach to generate tests for gate delay faults. Unlike other known algorithms which try to generate a 'good' delay test the presented ...
111
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ICCAD
1991
IEEE
15 years 1 months ago
1991
IEEE
This paper presents an efficient algorithm for the generation of diagnostic test patterns which distinguish between two arbitrary single stuck-at faults. The algorithm is able to ...
67
Voted
DATE
2005
IEEE
15 years 3 months ago
2005
IEEE
— With increasing process fluctuations in nano-scale technology, testing for delay faults is becoming essential in manufacturing test to complement stuck-at-fault testing. Desig...