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86
Voted
VLSID
2009
IEEE
15 years 10 months ago
2009
IEEE
We present the automatic test pattern generator TIGUAN based on a thread-parallel SAT solver. Due to a tight integration of the SAT engine into the ATPG algorithm and a carefully ...
ET
2006
14 years 9 months ago
2006
We present an efficient built-in self-test (BIST) architecture for testing and diagnosing stuck-at faults, delay faults, and bridging faults in FPGA interconnect resources. The BIS...
DAC
1994
ACM
15 years 1 months ago
1994
ACM
A powerful combinational path sensitization engine is required for the efficient implementation of tools for test pattern generation, timing analysis, and delay fault testing. Path...
ITC
1996
IEEE
15 years 1 months ago
1996
IEEE
This paper describes test generation for delay faults caused by global process disturbances. The structural and spatial correlation between path delays is used to reduce the numbe...
DATE
2003
IEEE
15 years 2 months ago
2003
IEEE
Abstract : A novel design methodology for test pattern generation in BIST is presented. Here faults and errors in the generator itself are detected. Two different design methodolog...