18 search results - page 1 / 4 » Test Time Reduction Reusing Multiple Processors in a Network... |
DATE
2005
IEEE
15 years 3 months ago
2005
IEEE
The increasing complexity and the short life cycles of embedded systems are pushing the current system-onchip designs towards a rapid increasing on the number of programmable proc...
CASES
2008
ACM
14 years 11 months ago
2008
ACM
This paper proposes a combination of circuit and architectural techniques to maximize leakage power reduction in embedded processor on-chip caches. It targets cache peripheral cir...
VLSID
2004
IEEE
15 years 10 months ago
2004
IEEE
Recent advances on language based software toolkit generation enables performance driven exploration of embedded systems by exploiting the application behavior. There is a need fo...
72
Voted
ICCAD
2004
IEEE
15 years 6 months ago
2004
IEEE
— In this paper we investigate an effective approach to construct a linear decompression network in the multiple scan chain architecture. A minimal pin architecture, complemented...
90
Voted
DATE
2008
IEEE
15 years 4 months ago
2008
IEEE
Functional, instruction-based self-testing of microprocessors has recently emerged as an effective alternative or supplement to other testing approaches, and is progressively adop...