29 search results - page 3 / 6 » Test compaction for transition faults under transparent-scan |
104
Voted
DATE
2002
IEEE
15 years 4 months ago
2002
IEEE
Test sets for path delay faults in circuits with large numbers of paths are typically generated for path delay faults associated with the longest circuit paths. We show that such ...
69
Voted
DATE
1998
IEEE
15 years 3 months ago
1998
IEEE
We extend the subsequence removal technique to provide signi cantly higher static compaction for sequential circuits. We show that state relaxation techniques can be used to ident...
DATE
2007
IEEE
15 years 6 months ago
2007
IEEE
A high-level test synthesis (HLTS) method targeted for delay fault testability is presented. The proposed method, when combined with hierarchical test pattern generation for embed...
ICCD
2006
IEEE
15 years 8 months ago
2006
IEEE
This paper discusses an automated method to build scan chains at the register-transfer level (RTL) for powerconstrained at-speed testing. By analyzing a circuit at the RTL, where ...
PTS
2003
15 years 1 months ago
2003
The paper studies testing based on input/output transition systems, also known as input/output automata. It is assumed that a tester can never prevent an implementation under test ...