5855 search results - page 108 / 1171 » Test generation and minimization with |
ARITH
1999
IEEE
15 years 5 months ago
1999
IEEE
ICCAD
1999
IEEE
15 years 5 months ago
1999
IEEE
: Inductance of on-chip interconnects gives rise to signal overshoots and undershoots that can cause logic errors. By considering technology trends, we show that in 0.13
KBSE
1999
IEEE
15 years 5 months ago
1999
IEEE
ESEC
1999
Springer
15 years 5 months ago
1999
Springer
ATS
1998
IEEE
15 years 5 months ago
1998
IEEE
This paper aims at broadening the scope of hierarchical ATPG to the behavioral-level The main problem of using behavioral information for ATPG is the mismatch of timing models bet...