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ASYNC
1998
IEEE
15 years 5 months ago
1998
IEEE
None of the available minimizers for exact 2-level hazard-free logic minimization can synthesize very large circuits. This limitation has forced researchers to resort to heuristic...
VLSID
2003
IEEE
16 years 1 months ago
2003
IEEE
This paper introduces a Built-In Self Test (BIST) structure referred to as Universal BIST (UBIST). The Test Pattern Generator (TPG) of the proposed UBIST is designed to generate an...
103
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ACSD
2003
IEEE
15 years 5 months ago
2003
IEEE
In this paper test selection strategies in formal conformance testing are considered. As the testing conformance relation we use the ioco relation, and extend the previously prese...
111
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VLSID
2005
IEEE
16 years 1 months ago
2005
IEEE
Abstract-- We present two-dimensional (space/time) compression techniques that reduce test data volume and test application time for scan testing of intellectual property (IP) core...
112
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CP
2005
Springer
15 years 7 months ago
2005
Springer
This paper describes an efficient, complete approach for solving a complex allocation and scheduling problem for Multi-Processor System-on-Chip (MPSoC). Given a throughput constra...