5855 search results - page 46 / 1171 » Test generation and minimization with |
VTS
2005
IEEE
15 years 6 months ago
2005
IEEE
This paper presents a pseudo-functional BIST scheme that attempts to minimize the over-testing problem of logic BIST for delay and crosstalk-induced failures. The over-testing pro...
125
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COMPSAC
2010
IEEE
14 years 11 months ago
2010
IEEE
An important goal of automatic testing techniques, including random testing is to achieve high code coverage with a minimum set of test cases. To meet this goal, random testing res...
106
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DSD
2009
IEEE
15 years 8 months ago
2009
IEEE
—Long test application time and high temperature have become two major issues of system-on-chip (SoC) test. In order to minimize test application times and avoid overheating duri...
123
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ATS
2005
IEEE
15 years 7 months ago
2005
IEEE
11 Due to the increasing test data volume needed to test corebased System-on-Chip, several test scheduling techniques minimizing the test application time have been proposed. In co...
SEFM
2003
IEEE
15 years 6 months ago
2003
IEEE
The Specification and Description Language (SDL) together with its associated tool sets can be used for the generation of Tree and Tabular Combined Notation (TTCN) test cases. Sur...