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EVOW
2008
Springer
15 years 3 months ago
An Evolutionary Methodology for Test Generation for Peripheral Cores Via Dynamic FSM Extraction
Traditional test generation methodologies for peripheral cores are performed by a skilled test engineer, leading to long generation times. In this paper a test generation methodolo...
Danilo Ravotto, Ernesto Sánchez, Massimilia...
DAC
2003
ACM
15 years 6 months ago
Test generation for designs with multiple clocks
To improve the system performance, designs with multiple clocks have become more and more popular. In this paper, several novel test generation procedures are proposed to utilize ...
Xijiang Lin, Rob Thompson
DATE
1999
IEEE
120views Hardware» more  DATE 1999»
15 years 5 months ago
FreezeFrame: Compact Test Generation Using a Frozen Clock Strategy
Test application time is an important factor in the overall cost of VLSI chip testing. We present a new ATPG approach for generating compact test sequences for sequential circuits...
Yanti Santoso, Matthew C. Merten, Elizabeth M. Rud...
DATE
1997
IEEE
100views Hardware» more  DATE 1997»
15 years 5 months ago
On the generation of pseudo-deterministic two-patterns test sequence with LFSRs
Many Built-In Self Test pattern generators use Linear Feedback Shift Registers (LFSR) to generate test sequences. In this paper, we address the generation of deterministic pairs o...
Christian Dufaza, Yervant Zorian
ACL
2006
15 years 2 months ago
FAST - An Automatic Generation System for Grammar Tests
This paper introduces a method for the semi-automatic generation of grammar test items by applying Natural Language Processing (NLP) techniques. Based on manually-designed pattern...
Chia-Yin Chen, Hsien-Chin Liou, Jason S. Chang