In this paper we report an automatic test pattern generator that can handle designs with one million gates or more on medium size workstations. Run times and success rates, i.e. t...
Sandip Kundu, Leendert M. Huisman, Indira Nair, Vi...
A new method for state justi cation is proposed for sequential circuit test generation. The linear list of states dynamically obtained during the derivation of test vectors is use...
Michael S. Hsiao, Elizabeth M. Rudnick, Janak H. P...
This paper presents a comparative analysis of neural networks, simulated annealing, and genetic algorithms in the determination of input patterns for testing analog circuits. The ...
We present our experience in automatically deriving a detailed test case plan exclusively using the UML diagrams developed during the analysis and design phases. We consider in pa...
The problem of testing from an extended finite state machine (EFSM) can be expressed in terms of finding suitable paths through the EFSM and then deriving test data to follow the ...
Abdul Salam Kalaji, Robert M. Hierons, Stephen Swi...