5855 search results - page 94 / 1171 » Test generation and minimization with |
ASPDAC
2006
ACM
15 years 7 months ago
2006
ACM
– An instruction set level reference model was developed for the development of synergistic processing unit (SPU) , which is one of the key components of the cell processor [1][2...
112
click to vote
IPPS
1998
IEEE
15 years 5 months ago
1998
IEEE
In this communication Simulated Annealing and Genetic Algorithms, are applied to the graph partitioning problem. These techniques mimic processes in statistical mechanics and biol...
VTS
1998
IEEE
15 years 5 months ago
1998
IEEE
This paper presents simulation evidence supporting the use of bit transition maximization techniques in the design of hardware test pattern generators TPGs. Bit transition maximiz...
ICST
2010
IEEE
14 years 12 months ago
2010
IEEE
Abstract—In this paper we introduce Timed Moore Automata, a specification formalism which is used in industrial train control applications for specifying the real-time behavior ...
ISSRE
2007
IEEE
15 years 3 months ago
2007
IEEE
Model-checkers are powerful tools that can find individual traces through models to satisfy desired properties. These traces provide solutions to a number of problems. Instead of...