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» Test pattern generation based on arithmetic operations
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DAC
1997
ACM
15 years 6 months ago
Analysis and Evaluation of Address Arithmetic Capabilities in Custom DSP Architectures
—Many application-specific architectures provide indirect addressing modes with auto-increment/decrement arithmetic. Since these architectures generally do not feature an indexe...
Ashok Sudarsanam, Stan Y. Liao, Srinivas Devadas
124
Voted
MICS
2007
100views more  MICS 2007»
15 years 1 months ago
A New Method for Real Root Isolation of Univariate Polynomials
A new algorithm for real root isolation of univariate polynomials is proposed, which is mainly based on exact interval arithmetic and bisection method. Although exact interval arit...
Ting Zhang, Bican Xia
DATE
2005
IEEE
127views Hardware» more  DATE 2005»
15 years 7 months ago
A Novel Low-overhead Delay Testing Technique for Arbitrary Two-Pattern Test Application
— With increasing process fluctuations in nano-scale technology, testing for delay faults is becoming essential in manufacturing test to complement stuck-at-fault testing. Desig...
Swarup Bhunia, Hamid Mahmoodi-Meimand, Arijit Rayc...
119
Voted
ITC
2003
IEEE
120views Hardware» more  ITC 2003»
15 years 7 months ago
Test Vector Generation Based on Correlation Model for Ratio-Iddq
For ratio-Iddq testing, the test performance is significantly affected by the correlation between two currents of different input patterns as process parameters vary. In this p...
Xiaoyun Sun, Larry L. Kinney, Bapiraju Vinnakota
ETS
2009
IEEE
79views Hardware» more  ETS 2009»
14 years 11 months ago
Concurrent Self-Test with Partially Specified Patterns for Low Test Latency and Overhead
Structural on-line self-test may be performed to detect permanent faults and avoid their accumulation. This paper improves concurrent BIST techniques based on a deterministic test ...
Michael A. Kochte, Christian G. Zoellin, Hans-Joac...